Memory Management and Virtual Memory Virtual Memory

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Introduction to Virtual Memory and Memory ManagementARMAdvanced RISC Machines


Physical Memory A computer system will probably contain several different types of memory devices. The Memory Management mechanism must access all available memory in, apparently , the same way as seen by user code.Slow D/VRAM,ROMDISC or other v. slow devicePhysical Address SpaceFast SRAM,ROMFast memory, on chip or off, is expensive. Most memory will be slow (eg disc) Making the system think all memory is in the one place, and of the one type employs Virtual Memory.


Virtual memoryVirtual Memory Fast RAM/ROMSlow RAM/ROMDISC or other v. slow device=Seen by the system. e.g. 4GB Virtual Address Space Physical Address Space e.g.. 180MB 4MB 1MB* The physical memory may be smaller than the - total CPU address space - the total required for all user code and data. * Create a VIRTUAL memory space, mapping into the Physical memory space.


Virtual AddressesMapping of virtual addresses to physical addresses via a page table Memory mapping or address translation


Memory management -overview"Memory Management Units" allow the processor to use external memory mapped into a virtual address space. allows protection schemes to be implemented control system when the physical memory is less than the virtual memory control system when physical is greater than the virtual memory Efficient memory usage ( Eg: defragmentation ) This added complexity may bring problems: increased die size a “single” access may require up to three accesses to translate the address and get the data.


An exampleThe Memory Management hardware resolves: the mapping from virtual to physical memory the access rights of the current process against those of the memory requested.Protection & AbortsVRAMRAMROMRAMRAMProcess AVirtual MemoryPhysical Memory Translation and checking mechanism.TLBTranslation TablesManagerProcess BProcess CMMU


Page TablesPage tables contain the mapping of the Virtual to Physical Addresses The Page table must be read before the translation can take place Extra read cycles are required to access the page tables A single read could require up to 3 accesses to memory to get the dataProtectionAddress MappingPage Table EntryThe amount of information that can be stored about the protection is limited by the size of the page.


Segments and PagesMemory (physical or virtual) is divided into Segments or Pages Segments are variable size blocks Largest segment could be 4GBytes Smallest segment could be 1 Byte Requires two words per address More difficult to handle as must find contiguous unused block of memory to replace a segment Pages are fixed length blocks Typically 512 to 8192 bytes Require one word per address Easier to handle as all blocks are the same size Less wasted storage space as it is easier to store the smaller pages Compromise is Paged Segments Each segment is is an integral number of pages


Memory management structuresTwo main operations are required from a memory management system: Translation : Finding the location of the real, physical, address of the required memory from the virtual address. Protection : Confirmation that this location is eligible for access under the current privilege ARM has split the two operations. This allows the size of the units of address location or translation to be different from those of protection


Translation Lookaside Buffers ( 1 )A data read could take up to three accesses to memory Slow when trying to read dataMMUPhysical MemoryVirtual MemoryPage TablesData Requireddescriptor 1descriptor 2Access Real Data


Translation Lookaside Buffers (2 )The Translation Lookaside Buffers effectively cache the last transactions so the accesses to the page tables are not needed.MMUPhysical MemoryVirtual MemoryPage TablesAccess Real DataTLB’s


The Translation Page TablesIf the TLB misses, the translation walk hardware accesses the Translation Page Tables, kept in physical memory The translation will be satisfiedTranslation Table (level 2)L2PTSector AccessPage accessBase of Translation Table held in TT Base Register of MMU. Must reside on 16KByte boundaries Translation information returned to TLB.Translation Tables (in physical memory)Translation Table (level 1)Physical memoryTo MMU

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Last Updated: 8th March 2018

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